OVERVIEW

The MSquare LPDDR5X/4X PHY is a transceiver physical layer IP interface solution designed for ASICs and SOCs. Compatible with the universal IP protocol DFI 5.0, it can operate at the data rate up to 8533Mbps with 16-bit data width per channel. With flexible configuration options, the LPDDR5X/4X PHY can be used in a variety of mobile applications supporting LPDDR5X, LPDDR5 and LPDDR4X SDRAMs. With its hybrid analog/digital architecture, MSquare's IP delivers low power consumption, compact footprint, and robust performance, making it well-suited for LPDDR5X/4X PHY applications.

HIGHLIGHTS

Compatible with JEDEC standard LPDDR4X , LPDDR5 and LPDDR5X SDRAMs

Supports for data rates up to 8533 Mbps

DFI5.0 for PHY and Controller interface

Supports PHY independent training mode by Processor

Supports Data Bus Inversion(DBI) mod

Supports 4 trained frequencies

Supports BIST and LOOPBACK mode

Supports background tracking for PVT compensation

Supports bypass mode for low-power at low-speed scenario

Compliant with JEDEC standard JESD209-4D and JESD209-5B