OVERVIEW

The MSquare LPDDR4X PHY is a transceiver physical layer IP interface solution designed for ASICs and SOCs. Compatible with the universal IP protocol DFI 4.0, it can operate at the data rate up to 4267Mbps with 16-bit data width per channel. As depicted in Figure 1, the LPDDR4X PHY block diagram for system application includes data and address transmit path, receiver data path and PLL block, and more. With its hybrid analog/digital architecture, MSquare's IP delivers low power consumption, a compact footprint, and robust performance, making it well-suited for LPDDR4X applications.

HIGHLIGHTS

Compliant with DFI 4.0 for PHY and control interface

Compatible LPDDR4X up to 4267Mbps

Flexible channel architecture

Supports PHY independent training mode using an embedded processor

Supports Dual Rank

DVFS supporting 4  trained frequencies

Supports BIST and loopback mode

Supports background tracking for PVT compensation

Integrated low-jitter PLL and DLL

Compliant with JEDEC standard JESD209-4C