• Product Introduction
SerDes

OVERVIEW

SerDes PHY IP provides high-performance, multi-lane capability and low-power architecture for the high-bandwidth applications. The SerDes IP has supported data rates from 1.25G to 10.3125Gbps including XFI, SFI, 10GBASE-Kr, CEI, XAUI, USXGMII, 



HIGHLIGHTS

Supports 1.25G to 10.3125Gbps data rates and compact die area (<0.55mm² for 2-lane)

Supports >20dB channel loss

Supports RX loss-of-signal detect

Supports X1, X2, and X4 lanes

Accessible register controls allows user specific optimization of critical parameters (e.g. TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)

Supports both FOM for Link-EQ Training

Supports robust BIST functions for mass production tests

Supports Wire-Bond and Flip-Chip packages

Available in 7nm, 12nm, 14nm, 16nm, and 28nm process nodes

Series upgrade products
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