OVERVIEW

MSquare's USB 3.2 PHY IP is designed based on the USB 3.2 Gen2x1 and USB2.0 specifications from the USB Implementer Forum, delivers up to 10Gbps bandwidth. This high bandwidth capability is particularly beneficial for consumer industrial video applications, display and docking applications, cloud computing and automotive applications. 

As a leading supplier of USB IP, MSquare provides customers with low-power, compact, and high-performance IP designed with unique hybrid analog/digital architecture. This IP supports all USB functions, including transceivers for 10G, 5G, 480M, 12M, and 1.5Mbps, and provides complete deliverables that simplify SOC integration and silicon validation. Our IP is available in a wide variety of process nodes from 40nm to 6/7nm. With compact die size and low pad count, this IP increases the product competitiveness in USB market. 

HIGHLIGHTS

Fully compliant USB 3.2 Gen2x1 with PIPE 4.3 and USB2.0 with UTMI+ interface

Supports both host, peripheral and dual role application

Supports 10/12/25/30/19.2/24/27/40MHz crystal oscillator or clock inputs

Supports TX 3-Tap FFE and RX CTLE+1-Tap DFE for SS+

Integrates an active switch to support the orientation-less connection with USB Type-C connector

Provides an auxiliary CC module IP to support USB Type-C related functions

Provides robust BIST functions for mass production tests

Supports Crystal pad for clock source (Need to use with the XTAL module IP of MSquare)

Supports OTG application (Need to use with the IDPAD module IP of MSquare)

USB PHY IP is available in 7nm, 12nm, 16nm, 28nm and 40nm process 

Supports both wire-bond and flip-chip package type

Supports wire-bond package type